8k mem driver download

The receiver only re- 8. Note that an In this mode data is transferred synchronously with the implicit assumption is made for full duplex USART operation clock. Data is transmitted on the rising edge and received on that the framing formats are the same for the transmitter and the falling edge of the synchronous clock.

Framing Formats 8. Internally, the basic baud clock is created from the oscillator frequency The USART is capable of generating interrupts. Both interrupts have individual interrupt vectors. Two Figure Note that the bit terrupt vector. The ister PSR. PSR is cleared upon reset. There are many ways to calculate the two divisor factors, but one particularly The interrupt from the receiver is set pending, and remains effective method would be to achieve a 1. To quency coming out of the first stage.

The 1. The 16x clock is then divided by 16 to provide the rate for the serial shift registers of the transmitter and receiver. Baud Rate Divisors Prescaler Prescaler 1. In the Prescaler Factors 15 The idle timer T0 generates a fixed tc delay As an example, considering Asynchronous Mode and a CKI to ensure that the oscillator has indeed stabilized before clock of 4. The user has to con- sider this delay when data transfer is expected immediately 4.

The 2. For a baud rate of e. In this The divide by 16 is performed because in the asynchronous mode, data that is transmitted is immediately received.

This mode, the input frequency to the USART is 16 times the feature allows the processor to verify the transmit and re- baud rate. Where: BR is the Baud Rate 8. The data format for transmission must also be selected as Note: In the Synchronous Mode, the divisor 16 is replaced by two.

This Mode supports a Using the above equation N x P can be calculated first. Now IDLE modes are entered. The lection of this Mode. The register TSFT bits are set to one. The receiver registers value of the ninth bit received is obtained by reading RBIT9. Start bit of a character is detected at the RDX L3 pin. This feature is obtained by using the Multi-Input Wakeup scheme 9. This a pair of inputs positive and negative and an output. The follow- register. The Wakeup trigger condition is then selected to be ing is the Port F assignment: high to low transition.

F6 Comparator2 output If the device is halted and crystal oscillator is used, the Wakeup signal will not start the chip running immediately F5 Comparator2 positive input F4 Comparator2 negative input F3 Comparator1 output F2 Comparator1 positive input 33 www.

The Comparator Select Register is cleared with reset, result- F1 Comparator1 negative input ing in the comparators being disabled. The configuration of the the comparators, read the outputs of the comparators inter- CMPSL register is as follows: nally, and enable the outputs of the comparators to the pins. The VIS instruction may be used to vector to the will read as 0 if the comparator is not enabled appropriate service routine from location 00FF Hex.

Each of the 13 maskable inputs has a fixed arbitration rank- ing and vector. Note: If the user attempts to use the comparator output immediately after enabling the comparator, an incorrect Figure 25 shows the Interrupt Block Diagram.

At least one instruction cycle should pass between these operations. The use of a direct addressing mode instruction for either of these two operations will guar- antee this delay in the software. If All interrupts other than the Software Trap are maskable.

The pending bit is set to 1 when the interrupt condition occurs. The state of the interrupt enable bit, com- Within a specific interrupt service routine, the associated bined with the GIE bit determines whether an active pending pending bit should be cleared. This is typically done as early flag actually triggers an interrupt. All of the maskable inter- as possible in the service routine in order to avoid missing rupt pending and enable bits are contained in mapped con- the next occurrence of the same type of interrupt event.

Thus, if the same event occurs a second time, even while the first occurrence is still being serviced, the second occur- A maskable interrupt condition triggers an interrupt under the rence will be serviced immediately upon return from the following conditions: current interrupt routine.

The enable bit associated with that interrupt is set. An interrupt service routine typically ends with an RETI instruction. This instruction sets the GIE bit back to 1, pops 2. The GIE bit is set. Program execution then proceeds with 3. The device is not processing a non-maskable interrupt. If there are any valid interrupts maskable interrupt must wait until that service routine is pending, the highest-priority interrupt is serviced immedi- completed. An interrupt is triggered only when all of these conditions are If different maskable interrupts meet these conditions simultaneously, the highest The general interrupt service routine, which starts at address priority interrupt will be serviced first, and the other pending 00FF Hex, must be capable of handling all types of inter- interrupts must wait.

The VIS instruction, together with an interrupt vector table, directs the device to the specific interrupt handling Upon Reset, all pending bits, individual enable bits, and the routine based on the cause of the interrupt. GIE bit are reset to zero. Thus, a maskable interrupt condi- tion cannot trigger an interrupt until the program enables it by VIS is a single-byte instruction, typically used at the very setting both the GIE bit and the individual enable bit.

When beginning of the general interrupt service routine at address enabling an interrupt, the user should consider whether or 00FF Hex, or shortly after that point, just after the code used not a previously activated set pending bit should be ac- for context switching. The VIS instruction determines which knowledged.

If, at the time an interrupt is enabled, any enabled and pending interrupt has the highest priority, and previous occurrences of the interrupt should be ignored, the causes an indirect jump to the address corresponding to that associated pending bit must be reset to zero prior to en- interrupt source. The jump addresses vectors for all pos- abling the interrupt. Otherwise, the interrupt may be simply sible interrupts sources are stored in a vector table.

A maskable interrupt is active if its asso- The vector table may be as long as 32 bytes maximum of 16 ciated enable and pending bits are set. However, if the VIS instruction is An interrupt is an asychronous event which may occur be- at the very top of a byte block such as at 00FF Hex , fore, during, or after an instruction cycle.

Any interrupt which the vector table resides at the top of the next byte block. If the VIS interrupt is acknowledged. The GIE bit is automatically reset to zero, preventing any specific interrupt service routine somewhere in the 32 kbyte subsequent maskable interrupt from interrupting the cur- memory space. Each vector occupies two bytes of the vector rent service routine. This feature prevents one maskable table, with the higher-order byte at the lower address. The interrupt from interrupting another one being serviced.

The vector of the maskable interrupt with the lowest rank is located to 2. The address of the instruction about to be executed is 0yE0 higher-order byte and 0yE1 lower-order byte. The pushed onto the stack. The Software Trap has the highest 3. The causing a jump to that program memory location. The device requires seven instruction cycles to perform the actions listed above.

Table 6 shows the types of interrupts, the interrupt arbitration ranking, and the locations of the corresponding vectors in If the user wishes to allow nested interrupts, the interrupts the vector table. If nested interrupts are allowed, locations of the specific interrupt service routines.

For ex- caution must be exercised. The user must write the program in such a way as to prevent stack overflow, loss of saved context information, and other unwanted conditions. The interrupt service routine stored at location 00FF Hex should use the VIS instruction to determine the cause of the 35 www.

In this case, interrupts will be then the vector location 0yFE and -0yFF should contain the serviced in turn until no further interrupts are pending and data 03 and 10 Hex, respectively. After testing the GIE bit to interrupt occurs and the VIS instruction is executed, the ensure that execution is not erroneous, the routine should program jumps to the address specified in the vector table.

The interrupt sources in the vector table are listed in order of rank, from highest to lowest priority. Upon return interrupts with a penalty of fewer than ten instruction cycles from the interrupt service routine, the next highest-level if no further interrupts are pending.

To ensure reliable operation, the user should always use the If the VIS instruction is executed, but no interrupts are en- VIS instruction to determine the source of an interrupt.

Al- abled and pending, the lowest-priority interrupt vector is though it is possible to poll the pending bits to detect the used, and a jump is made to the corresponding address in source of an interrupt, this practice is not recommended. The the vector table. This is an unusual occurrence, and may be use of polling allows the standard arbitration ranking to be the result of an error.

It can legitimately result from a change altered, but the reliability of the interrupt system is compro- in the enable bits or pending flags prior to the execution of mised. The polling routine must individually test the enable the VIS instruction, such as executing a single cycle instruc- and pending bits of each maskable interrupt. If a Software tion which clears an enable flag at the same time that the Trap interrupt should occur, it will be serviced last, even pending flag is set.

It can also result, however, from inad- though it should have the highest priority. Under certain vertent execution of the VIS command outside of the context conditions, a Software Trap could be triggered but not ser- of an interrupt. The default VIS interrupt vector can be useful for applica- Problems such as this can be avoided by using VIS tions in which time critical interrupts can occur during the instruction.

VIS and the vector table must be located in the same byte block except if VIS is located at the last address of a block. In this case, the table must be in the next block. This vector is read from program memory and placed into the PC which is now pointed to the 1st instruction When the VIS instruction is executed it activates the arbitra- of the service routine of the active interrupt with the highest tion logic.

The arbitration logic generates an even number arbitration ranking. For example, if instruction. Figure 27 shows a flowchart for the VIS instruc- the software trap interrupt is active, FE is generated. If the tion. If the only active The non-maskable interrupt pending flag is cleared by the interrupt is software trap, than E0 is generated. VIS Operation 37 www.

VIS Flowchart www. This will allow To avoid problems such as this, the This pending flag is not memory- mapped and cannot be accessed directly by the software. If a The pending flag is reset to zero when a device Reset programming error or hardware condition brownout, power occurs. When the non-maskable interrupt occurs, the asso- supply glitch, etc.

The interrupt service routine way for it to be cleared, all other interrupts will be locked out. There is no harm in executing extra RPND instructions in these parts of the program. This can happen in a same service subroutine. Some examples of causes are listed below. The interrupt from Port L shares logic with the wake up circuitry.

The register WKEN allows interrupts from Port L to If the program counter incorrectly points to a memory loca- be individually enabled or disabled. The register WKEDG tion beyond the available program memory space, the non- specifies the trigger condition to be either a positive or a existent or unused memory location returns zeroes which is negative edge. A separate global pending flag is not condition such as a brownout or power supply glitch. The Software Trap has the highest priority of all interrupts.

If he user is used to inhibit other interrupts and to direct the elects to disable the interrupt, then the device will restart program to the ST service routine with the VIS instruction.

The Software Trap indicates an unusual or unknown error condition. Generally, returning to normal execution at the Therefore, the Software Trap service routine should The device uses the following types of interrupts, listed reinitialize the stack pointer and perform a recovery proce- below in order of priority: dure that restarts the software at some known point, similar to a device Reset, but not necessarily performing all the 1.

The Software Trap non-maskable interrupt, triggered by same functions as a device Reset. The routine must also the INTR 00 opcode instruction. This interrupt service rou- Otherwise, all other interrupts will be locked out. To the tine can be interrupted only by another Software Trap. Software Trap can be determined. Maskable interrupts, triggered by an on-chip peripheral If the user wishes to return to normal execution from the block or an external device connected to the device.

This is because the return address stored on maskable interrupt routine in progress can be inter- the stack is the address of the INTR instruction that triggered rupted by the non-maskable interrupt request. A the interrupt. The program must skip that instruction in order maskable interrupt routine should end with an RETI to proceed with the next one.

Otherwise, an infinite loop of instruction or, prior to restoring context, should return to Software Traps and returns will occur. This is particularly useful when exiting long interrupt service routiness if the time Programming a return to normal execution requires careful between interrupts is short. In this case the RETI instruc- consideration. This The lower limit of the service window is fixed at instruc- pull-up is sufficient to serve as the connection to VCC for tion cycles.

Upon user to pick an upper limit of the service window. This flex- trigger threshold. The key data is fixed at Bit 0 of be ignored. TABLE 8. This equates to a clock input rate on CKI of greater or equal to kHz.

Reading of undefined ROM gets zeroes. Any attempt to and Hex which are undefined RAM. Executing from undefined ROM. Figure 28 IDLE counter toggles every instruction cycles. Figure 28 shows how Master mode of operation.

In the in the idle phase. Table 10 details the register. In the slave mode, the shift clock stops after 8 clock pulses. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to shift. This ensures that all data bits sent by the The SK pin must be selected as an input and the SO pin is selected as an output pin by setting and The device allows either the normal SK clock or an alternate resetting the appropriate bits in the Port G configuration phase SK clock to shift data in and out of the SIO register.

In register. Table 11 summarizes the settings required to enter both the modes the SK idle polarity can be either high or low. The polarity is selected by bit 5 of Port G data register. Bit 6 of Port G configuration register selects the SK edge.

Bit Config. Bit Fun. Reading memory locations from other Seg- ments i. It contains information about the instruction set Decrementing features, addressing modes and types. Each descrip- The strength of the instruction set is based on the following tion includes an example of an assembly language instruc- features: tion using the described addressing mode.

The memory address is specified directly as a byte in size. Register B or X Indirect. This allows for greater effi- X A,[B] ciency both in cycle time and program code in loading, walking across and processing fields in data memory. The relevant memory address is specified memory addresses. Each method is called an addressing by the contents of the B Register or X register pointer mode.

These modes are classified into two categories: op- register. The pointer register is automatically incremented erand addressing modes and transfer-of-control addressing or decremented after execution, allowing easy manipulation modes.

Operand addressing modes are the various meth- of memory blocks with software loops. Transfer-of-control addressing modes are used in register serves as the pointer, and whether the pointer is to conjunction with jump instructions to control the execution be incremented or decremented.

An instruction Memory Before After can specify an address directly by supplying the specific Accumulator 03 Hex 62 Hex address, or indirectly by specifying a register pointer. The Memory Location 62 Hex 03 Hex contents of the register or in some cases, two registers Hex point to the desired memory location.

In the immediate B Pointer 05 Hex 06 Hex mode, the data byte to be used is contained in the instruction itself. Each addressing mode has its own advantages and disad- vantages with respect to flexibility, execution speed, and program compactness. Not all modes are available with all instructions.

The Load LD instruction offers the largest number of addressing modes. The data for the operation follows the instruc- tion opcode in program memory.

In assembly language, the number sign character indicates an immediate operand. In this 1-byte instruction, six bits of the instruction opcode specify the distance of the jump from the Immediate Short. This is a special case of an immediate current program memory location. The distance of the jump instruction. The upper nibble of the B register is reset to binary.

In this 2-byte instruction, 12 bits of the Indirect from Program Memory. This is a special case of instruction opcode specify the new contents of the Program an indirect instruction that allows access to data tables Counter. The upper three bits of the Program Counter re- stored in program memory.

For purposes of accessing pro- gram memory, the contents of the Accumulator and PCL are This restriction is relevant only in devices using more than exchanged. The data pointed to by the Program Counter is one 4 kbyte program memory space.

In this 3-byte instruction, 15 bits of Memory Before After the instruction opcode specify the new contents of the Pro- 04 Hex 04 Hex gram Counter. However, Jump instructions can be used to change the PCL normal execution sequence. Several transfer-of-control ad- dressing modes are available to specify jump addresses. Jump Indirect. In this 1-byte instruction, the lower byte of the jump address is obtained from a table stored in program A change in program flow requires a non-incremental memory, with the Accumulator serving as the low order byte change in the Program Counter contents.

The Program of a pointer into program memory. For purposes of access- Counter consists of two bytes, designated the upper byte ing program memory, the contents of the Accumulator are PCU and lower byte PCL. The data pointed to by the is not used, leaving 15 bits to address the program memory.

Different addressing modes are used to specify the new address for the Program Counter. The choice of addressing Example: Jump Indirect mode depends primarily on the distance of the jump.

Farther jumps sometimes require more instruction bytes in order to JID completely specify the new Program Counter contents. The addressing mode determines the Memory Before After source of the data. Other logical operations can be performed by combining these basic operations.

For ex- The instruction set contains a wide variety of instructions. Skipped instructions are The Accumulator bit manipulation instructions allow the user to shift the Accumulator bits and to swap its two nibbles.

The Jump to Subroutine instructions save the The conditional instruction test a condition. If the condition is Program Counter contents on the stack before jumping; the true, the next instruction is executed in the normal manner; if Return instructions pop the top of the stack back into the the condition is false, the next instruction is skipped. Program Counter. No-Operation NOP Note: The VIS is a special case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter PC in order to jump to the associated interrupt service routine.

Jump absolute PC M version in- See Section 5. National is engaged with an international community of in- dependent 3rd party vendors who provide hardware and COP8 Development Productivity Tools software development tool support. Code Generation tool. Up-to-date information, selec- on-chip peripheral. Application specific code can be in- tion guides, free tools, demos, updates, and purchase infor- serted for customization using the integrated editor.

In- Windows based development COP8. Re- supply. Package-specific probes and surface mount altime target design environments with a selection of adaptors are ordered separately. Programming Environments adapters are extra. Includes a fully licensed vices. Plus Manuals, Applications for development and engineering use.

Software, and other COP8 technical information. Note: The following order numbers apply to the COP8 devices in this datasheet only. Go to the vendor's web site for current listings of distributors. Glanyrafon Enterprise Park, support kanda. And with HDMI 2. With the new Ultra Performance mode, you can crank up settings and resolutions for incredibly detailed 8K gaming.

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